Many switch or router products utilize multiple data interconnection cables or fiber links typically called high-speed inter-shelf links (HISLs). Such HISLs may provide gigabit and terabit bandwidth capacities between various components within a communications device. For example, on a routing switch platform, a HISL may be used to link an interface card or a line card circuit to a switch fabric.
In the interest of link throughput, these HISLs may employ parallel optical interfaces (PAROLI) and may not use framing overhead. Such framing is generally required for link synchronization using conventional methods. Additionally, since PAROLI interfaces comprise a plurality of parallel lines, these lines as well as corresponding circuits and buffers at either end require proper synchronization with respect to each other.
The link synchronization methods presently available either rely on framing, or may not provide satisfactory HISL link alignment of data segments carried on the PAROLI link. Also, known prior art solutions do not prevent cells from being sent through the HISL before it is fully synchronized, resulting in faulty performance.
Thus, there is a need for a method of synchronizing PAROLI links between components of a communications device which is more reliable and robust than methods available in the prior art.